RIP
Thanks to both of you!
JayKominek I believe the time values in your file are microseconds?
Yes they are (and the units should be specified).
JayKominek Something is wrong.
Ok, let's see what can I do to improve things.
xooorx JayKominek That's not nice gaussian noise you've got, there's some pretty awful structure. Something is wrong.
The ADC VREF on that board is just the switch mode power supply through an RC filter, which the datasheet admits is going to let through quite a lot of ripple/noise. It does also mention some things that can be done to reduce this.
The easiest thing would be to set the SMPS into PWM mode but that should have noticeable effect only at high load (and I don't think I am). However to do so I'd have to use GPIO23 which is not on a pin but on a test point on the back of the board and the datasheet mentions
TP4 GPIO23/SMPS PS pin (do not use)
without further elaborating why the "do not use" parenthetical. Alternatively, I had thought of powering it via batteries, but I believe the SMPS would kick in regardless to regulate the voltage to the desired level, so that sounded like a moot point (happy to be proved wrong about it). Using an external, high precision power supply was (probably still is) beyond my stamina level for this project, since I have none available and I'd have to find one, learn how to operate it, etc etc.
Moreover, while the noise is definitely there, it's mostly evident in the 12 bit sampling. Given this ADC ENOB is (slightly less than) 9, my eyes "automatically" deleted that information when reading the plots 🤣 -- probably too aggressively, since I now noticed that I did not pay much attention also to the about 2 bits of noise from the 8 bit sampling. Perhaps for the purpose of these tests I could just further reduce bit resolution and see what happens…. I'll think about it in the coming weekends.
Meanwhile, if @xooorx and @luns could chime in about the following (even with a "you can't say") that would made this part of my experimentation more clear
RIP If with S-G we don't need such a fast sample rate that is great news, since only very few ADC converters support that, and even then with limitations. However I know how to make a back-of-the-envelope estimate of the needed minimum sample rate for the comparator approach (*) but I am not sure how to do that estimate with S-G. Do you?
Thanks again everybody!








